1. Technical Field
The present invention relates to circuit routing in general, and, in particular, to a method and system for performing global routing on an integrated circuit design.
2. Description of Related Art
Routing is a key stage within a very-large scale integrated circuit (VLSI) design process. Since routing directly affects interconnect properties (such as wire length, routability, etc.), routing plays a critical role in the overall performance of a VLSI design. With nanometer interconnects, the manufacturability and variability issues, such as antenna effect, copper chemical-mechanical polishing (CMP), subwavelength printability, and yield loss due to random defects, are becoming a growing concern for VLSI designers. Hence, routing also plays a major role in terms of manufacturing closure.
Global routing, as its name implies, is the stage of routing that plans the approximate routing path of each net within a VLSI design in order to reduce the complexity of routing task that is eventually performed by a detailed router. Thus, global routing has significant impacts on wire length, routability and timing. Optimizing the wire density distribution during global routing can improve overall manufacturability such as less post-CMP topography variation, less copper erosion/dishing, and less optical interference for better printability. In addition, with faster global routing, more accurate interconnect information (such as wirelength and congestion) can be fed back to placement or other early physical synthesis engines for achieving better design convergence.
Consequently, it would be desirable to provide an improved method and system for performing global routing on a VLSI design.